1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices and, more particularly, to an electrically programmable and erasable read only memory. The invention relates more specifically to a flash memory including memory cells each comprised of one floating gate type transistor.
2. Description of the Background Art
One of semiconductor memory devices for storing information therein in a nonvolatile manner is called a flash memory. In the flash memory, all memory cells in a memory array are simultaneously put in an erase state during an erasing mode.
FIG. 9 is a diagram schematically showing a cross-sectional structure of one memory cell in a flash memory. With reference to FIG. 9, the memory cell includes n type impurity regions 102 and 104 formed on a surface of a p type semiconductor substrate 100, a floating gate 106 formed on a channel region 112 between the impurity regions 102 and 104 with a gate insulating film 110 interposed between the channel region and the floating gate, and a control gate 108 formed on the floating gate 106 with an interlayer insulation film 114 interposed therebetween. The floating gate 106 has its peripheries surrounded by the insulating films 110 and 114 and is brought into an electrically floating state. This memory cell has a structure of a MOS (Metal-Insulator-Semiconductor) transistor, in which the impurity regions 102 and 104 constitute a drain region and a source region, respectively.
FIG. 10 is a diagram showing an electrically equivalent circuit of the memory cell shown in FIG. 9. The control gate 108 has an electrode CG connected to a word line WL, and the impurity region 102 has a drain electrode D connected to a bit line BL. The impurity region 104 has its source electrode normally coupled via a source line S to a source potential generating circuit 116.
In the flash memory, memory cells of this type are arranged in rows and columns, and memory cells of one row are connected to a single word line WL, while memory cells of one column are provided on a single bit line BL. Data writing, erasing and reading with respect to the memory cell shown in FIGS. 9 and 10 are carried out as follows.
In writing, a high voltage Vpp of approximately 12 V is applied via the word line WL to the control gate 108, a voltage of approximately 6 V is applied via the bit line BL to the drain impurity region 102, and a ground potential is applied to the source impurity region 104 by the source potential generating circuit 116. In this state, a current flows from the drain impurity region 102 through the channel region 112 to the source impurity region 104. Charges in the current flowing from the drain impurity region 102 are excited by a high electric field formed near the drain impurity region 102, so that hot electrons are generated. The generated hot electrons cause avalanche breakdown, thereby generating a large amount of hot electrons. The hot electrons generated by the avalanche breakdown are accelerated to the floating gate 106 by the high voltage applied to the control gate 108 and are then trapped in the floating gate 106. In such a state that electrons are injected (trapped) into the floating gate 106, a threshold voltage Vth of this memory cell shifts in a positive direction.
In erasing, a ground potential is applied to the control gate 108, a high voltage Vpp of approximately 12 V is applied from the source potential generating circuit to the source impurity region 104, and the drain impurity region 102 is brought into a floating state. In this state, electrons are drawn out from the floating gate 106 through the gate insulating film 110 (very thin) to the source impurity region 104 due to a tunneling phenomenon. With the electrons drawn out from the floating gate 106, a threshold voltage Vth of this memory cell shifts in a negative direction.
As described above, the memory cell stores data "0" and "1" therein in accordance with the amount of electrons existing in the floating gate 106.
That is, as shown in FIG. 11, in the state where electrons are injected into the floating gate 106 (programmed state), its threshold voltage Vth shifts in the positive direction and the memory cell has a threshold voltage of Vr2. In the erase state where electrons are drawn out from the floating gate 106, its threshold voltage shifts in the negative direction and the memory cell has a threshold voltage Vr1. Normally, the programmed state where electrons are injected into the floating gate 106 is defined as a state where data "0" is stored, and the erase state where electrons are drawn out from the floating gate 106 is defined as a state where data "1" is stored.
In data reading, a ground potential is applied to the source impurity region 104, and a signal of a logic high level or "H" level which is approximately the same level as a supply voltage Vcc is transmitted via the word line WL to the control gate 108. In this state, this memory cell is in an OFF state when the memory cell stores data "0" therein, while the memory cell is an ON state when it stores data "1" therein. The bit line BL is supplied with a read potential, and data reading is carried out with a current driven sense amplifier detecting if a current flows in accordance with storage data of the memory cell.
With the memory cell thus structured, since data is stored in accordance with the amount of electrons existing in the floating gate 106, electrons are preserved in the floating gate 106 even if a power source is turned off. This enables a nonvolatile storage of information, and such a nonvolatile memory cell is utilized in various fields.
FIG. 12 is a diagram showing an overall structure of a conventional nonvolatile semiconductor memory device (flash memory), which is disclosed in, for example, Japanese Patent Laying-Open No. 2-10596. With reference to FIG. 12, a nonvolatile semiconductor memory device 200 includes a memory cell array 13 in which the memory cells having the structure shown in FIG. 9 are arranged in rows and columns. The nonvolatile semiconductor memory device 200 further includes an address latch 10 for latching applied address bits A0-Am to generate internal address bits, an X decoder 12 for decoding internal row address bits from the address latch 10 to select one row of the memory cell array 13, a Y decoder 11 for decoding internal column address bits from the address latch 10 to generate a column selecting signal for selecting a corresponding column of the memory cell array 13, and a Y gate circuit 14 which responds to the column selecting signal from the Y decoder 11 to connect a corresponding column of the memory cell array 13 to an internal data bus 123b or a data latch 15.
In this nonvolatile semiconductor memory device, data input/output is carried out in the units of 8 bits (one byte). Thus, the column selecting signal from the Y decoder 11 designates 8 columns in the memory cell array 13, and the Y gate circuit 14 responds to this column selecting signal to connect 8 columns to the internal data bus 123b or the data latch 15.
The nonvolatile semiconductor memory device 200 further includes an input/output buffer 6 coupled to an 8-bit bidirectional data bus 120, and a sensing circuit 7 for detecting the presence/absence of a current on the internal data bus 123 and reading memory cell data. An output of the sensing circuit 7 is transmitted to an output buffer included in the input/output buffer 6 and is then output as read data onto the data bus 120. In data writing (programming), the input/output buffer 6 generates internal data from data D0-D7 applied to the data bus 120 and applies the generated internal data via a data bus 123a to the data latch 15.
The nonvolatile semiconductor memory device 200 further includes, in order to execute erasing and programming of memory cell data, an instruction port controller 2 for generating various control signals in response to a write enable signal /WE, a chip enable signal /CE and a program high voltage Vpp, an erase voltage generating circuit 5 which responds to a control signal from the instruction port controller 2 to generate an erase voltage from the program high voltage Vpp and applies the generated erase voltage (a high voltage of approximately 12 V during an erasing operation) to respective sources of the memory cells in the memory cell array 13, a program voltage generating circuit 4 which responds to a control signal from the instruction port controller 2 to receive the program high voltage Vpp and generates and applies a program voltage to the Y decoder 11 and the X decoder 12, a CE /OE logic circuit 8 for controlling a data input/output operation of the input/output buffer 6 in response to the chip enable signal /CE and an output enable signal /OE, and an erase/program verification generating circuit 9 for generating a verify voltage during erasing/programming in response to a control signal from the instruction port controller 2.
The voltage output from the erase/program verification generating circuit 9 is applied to the X decoder 12, and during an erase/program verifying operation, the output voltage is transmitted via the X decoder 12 onto a selected word line in the memory cell array 13.
The instruction port controller 2 receives data applied from the input/output buffer 6 as an operation instructing signal in accordance with a combination of the states of the write enable signal /WE and the chip enable signal /CE, then decodes the received instruction signal and generates a necessary control signal. The instruction port controller 2 is rendered operative when the externally applied program high voltage Vpp is at a high voltage value of 12 V, while it is rendered inoperative when this program voltage Vpp is at a normal operation supply voltage level of 5 V. Instructions that can be decoded by the instruction port controller 2 are of 2.sup.n types (n is the number of data bits applied via the data bus 120).
This nonvolatile semiconductor memory device 200 externally receives an operating supply voltage Vcc of normally approximately 5 V, a potential Vss normally at a ground potential level, and a program high voltage Vpp. When the chip enable signal /CE attains a logic low level, this nonvolatile semiconductor memory device 200 is selected and executes a designated operation. That is, the instruction port controller 2 responds to the chip enable signal /CE of a low level to be ready to receive an instruction from the input/output buffer 6. The instruction port controller 2 receives the instruction from the input/output buffer 6 via the signal line 123a at a rising edge of the write enable signal /WE from a low level to a high level, and decodes the received instruction. When the program high voltage Vpp is 5 V, the instruction port controller 2 is rendered inoperative, and the nonvolatile semiconductor memory device 200 operates constantly only in a data reading mode.
Each of the data latch 15 and the address latch 10 responds to a strobe signal STB from the instruction port controller 2 to latch an applied signal in a program mode.
FIG. 13 is a block diagram showing structure of the instruction port controller shown in FIG. 12. With reference to FIG. 13, the instruction port controller 2 includes a WE.multidot.CE control logic circuit 231 which is activated in response to a low level of the chip enable signal /CE and generates an internal write enable signal CWE in accordance with the write enable signal /WE, an address clock generator 232 which is activated in response to the chip enable signal /CE and applies a latch timing signal STB to the address latch 10 shown in FIG. 12 in accordance with the internal write enable signal CWE, a status clock generator 233 for generating a clock signal in response to the internal write enable signal CWE, a status register 235 which responds to a clock signal from the status clock generator 233 to store therein, as an instruction code, data transmitted from the input/output buffer 6 onto the internal data bus 123a, and a clock generator 234 which is activated in response to an output signal from the status register 235 and generates an instruction clock signal and a data clock signal in response to the internal write enable signal CWE.
The clock generator 234 includes a data clock generator 234b for generating a strobe signal STB for providing data latch timing of a data latch (see FIG. 12), and an instruction clock generator 234a for generating an instruction clock signal for providing timing at which an instruction register 237 receives data on a data bus 223a as an instruction code.
The instruction port controller 2 further includes a status decoder 236 which decodes the instruction codes stored in the status register 235 and the instruction register 237, generates signals for controlling the operation of the erase voltage generator, the program voltage generator and the erase/program verification generator of FIG. 12 and also defines the operation of the address clock generator 232 and the status register 235.
An operation mode is designated by data applied via the data bus 123a in a write cycle which in turn is determined by the write enable signal /WE and the chip enable signal /CE. When the chip enable signal /CE attains a logic low level, the address clock generator 232 responds to a rising edge of the write enable signal /WE (i.e., a rising edge of the internal write enable signal CWE) to generate and apply an address strobe signal STB to the address latch 10 shown in FIG. 12. The address latch 10 responds to the applied address strobe signal STB to be brought into a latch state and latches an applied address.
At the rising edge of the write enable signal /WE, data is latched into the status register 235 and the instruction register 237 or the status register 235 and the data latch 15. The status decoder 236 decodes the data stored in the status register 235 and the instruction register 237 and drives corresponding circuits.
In an erasing mode, the erase voltage generator 5 responds to an output of the status decoder 236 to generate a program high voltage Vpp and applies the same to a source of each memory cell in the memory cell array 13.
The program voltage generator 4 selects the program high voltage Vpp in response to the output of the status decoder 236 in a programming mode (data writing) and applies the selected voltage to the X decoder 12 and the Y decoder 11. Accordingly, a column selecting signal and a word line driving signal from the Y decoder 11 and the X decoder 12 attain a high voltage Vpp level. In program verifying and erase verifying, the erase/program verification generating circuit 9 generates a verify voltage from the program high voltage Vpp and applies the same to the X decoder 12 in order to verify if programming is correctly made and erasing is executed. An operation will now be described.
In data reading, the chip enable signal /CE and the output enable signal /OE attain a low level, so that the CE /OE logic circuit 8 is activated. At that time, the CE /OE logic circuit 8 drives the output buffer included in the input/output buffer 6 at predetermined timing. The address latch 10 allows the applied address bits A0-Am to pass without being latched and generates internal address bits. The X decoder 12 and the Y decoder 11 decode the applied internal address bits and generate signals for selecting a row and a column of the memory cell array 13. In a reading mode, normally, selecting signals output from the X decoder 12 and the Y decoder 11 are at an operating supply voltage Vcc level. Data of selected memory cells in the memory cell array 13 are transmitted via the Y gate circuit 14 to the data bus 123b. The sensing circuit 7 reads memory cell data in response to the result as to whether or not a current flows through the data bus 123b, and applies the read data to the output buffer included in the input/output buffer 6. The output buffer generates external read data from the data read from the sensing circuit 7 under control by the CE /OE logic circuit 8 and transmits the generated external read data onto the 8-bit bidirectional data bus 120.
The erasing mode includes two cycles. In the first cycle, an erase code is written into the instruction register 237 and the status register 235. In the second cycle, an erase verify code is written into the status register 235. An erasing operation is started immediately after the erase verify code is written into the status register 235. The status decoder 236 first applies a control signal to the erase voltage generator 5 and applies a high voltage Vpp of 12 V from the erase voltage generator 5 to the respective sources of all the memory cells in the memory cell array 13, and the decoder 236 also sets all the outputs of the X decoder 12 at a ground potential. Accordingly, a high electric field is produced between the control gate and the source of each memory cell, and electrons stored in the floating gate are drawn to the source line in the form of a tunneling current.
Then, when an erase verifying code is written into the status register 235 and the instruction register 237, this erasing operation is ended and an address indicating the location of a memory cell to be verified is latched. Thus, the address strobe signal STB is generated from the address clock generator 232. The erase/program verification generator 9 generates an erase verify voltage from the program high voltage Vpp and applies the generated voltage to the X decoder 12.
The X decoder 12 transmits this erase verify voltage onto the word line. The Y decoder 11 connects a corresponding column in the memory cell array 13 via the Y gate circuit 14 to the data bus 123b. A threshold voltage of an erased memory cell is lower than the erase verify voltage, and an addressed memory cell is put in an ON state, so that data "1" is read in a normal case. Data of the addressed memory cell can be read via the input/output buffer 6 by an external device if the output enable signal OE is fallen to a low level. The external device is then able to determine in accordance with the read data whether or not the data of the memory cell is erased. This erase verifying operation is carried out for all addresses.
A programming operation includes two cycles similarly to the erasing operation. In the first cycle, a program instruction code is stored in the status register 235 and the instruction register 237. In the second cycle, the address latch 10 and the data latch 15 are brought into a latch state, so that the address bits A0-Am and program data are latched in the address latch 10 and the data latch 15, respectively. In the second cycle, when the write enable signal /WE rises, the status decoder 236 decodes instructions stored in the status register 235 and the instruction register 237, then applies a control signal to the program voltage generator 4 and starts programming.
The program voltage generator 4 responds to a signal from the instruction port controller 2 (the status decoder 236) to apply the program high voltage Vpp to the X decoder 12 and the Y decoder 11. The X decoder 12 and the Y decoder 11 decode the internal address bits latched in the address latch 10, then transmits a high voltage of the program high voltage Vpp level onto a corresponding word line in the memory cell array 13 and also applies a column selecting signal to the Y gate circuit 14. The data latch 15 transmits onto a bit line a write high voltage corresponding to data "0" Accordingly, a high voltage is applied to the control gate and the drain of the addressed memory cell, electrons are injected into the floating gate, and the data "0" is written.
Then, the programming is ended by writing a program verify instruction into the status register 235 and the instruction register 237, and an internal verify voltage for verifying data of a newly programmed memory cell is generated. The program verify voltage generated from the erase/program verification generator 9 is transmitted via the X decoder 12 onto a selected word line in the memory cell array 13. Data of the addressed memory cell of the memory cell array 13 is transmitted via the Y gate circuit 14 to the sensing circuit 7, and the transmitted data is detected and amplified by the sensing circuit 7 and then transmitted to the output buffer included in the input/output buffer 6.
With the output enable signal /OE set at a low level, the CE /OE logic circuit 8 activates the output buffer included in the input/output buffer 6 which transmits the data from the sensing circuit 7 onto the data bus 120. It is determined externally if data on the data bus 120 matches or mismatches the program data, and a determination is made as to whether data writing (programming) is carried out accurately. If the accurate programming is not made, then the program cycle is again executed and a programming is again carried out. A more detailed description will now be made on this erasing operation and the programming operation.
FIG. 14 is a flow chart showing the erasing operation of this nonvolatile semiconductor memory device. First, at the stage of initializing, a program high voltage Vpp is applied to the instruction port controller 2 to render the instruction port controller 2 operative (a step S2). Then, specific data (00H) is programmed for all bytes (data input/output is carried out in the units of byte and erasing is carried out also in the units of byte) (a step S4). This data programming is made in order to bring each memory cell into a write state and set the threshold voltage of each memory cell to be substantially equal. In addition, each counter is preset to a predetermined initial value (a step S6). This counter includes a counter for counting the number of time CUMTEW of the increase of an erase pulse width TEW, and a counter for counting the number of times PLSCNT by which erase pulses are generated. An address is set to 0.
Then, an erase setup instruction is written into the instruction port controller 2 (the status register 235 and the instruction register 237) (a step S8), and an erase instruction is subsequently written into the instruction port controller 2 (a step S10). An erasing with respect to all the memory cells is executed in accordance with the writing of the erase instruction (a step S12). After a predetermined time period has passed, it is determined that the erasing of the memory cells is completed, and an erase verify instruction is written into the instruction port controller 2 (the status register 235 and the instruction register 237) (a step S14). In accordance with this erase verify instruction, an erase verify voltage is generated from the erase/program verification generator 9 and then transmitted via the X decoder 12 onto a selected word line in the memory cell array (a step S16). When a predetermined time period has passed (time T2), data reading is carried out (a step S18).
If the read data is an erased data, then the data is "1". If the read data is an unerased data, then the data is "0". A determination is made as to whether this data is in the erased state or not in accordance with its value (a step S20). If the data indicates the unerased state, then an erase pulse width to be applied to erase the data is incremented by a predetermined value, and this incremented erase pulse width information is stored in the TEW counter (a step S22). A determination is first made as to whether the erase pulse width stored in the TEW counter reaches a maximum limit value, and subsequently, a determination is made as to whether the number by which the erase pulses are applied reaches a predetermined value (64 times) (a step S24). When the erase pulse application number PLSCNT reaches the predetermined value (64 times), it is determined that no erasing is allowed for that memory cell any more, and an erase error is stored (a step S26). When the erase pulse application number PLSCNT does not reach the predetermined value in the step S24, the processing returns to the step S8, in which the writing and erasing operation by the erase setup instruction and the erase instruction is carried out.
If the memory cell data is erased in the step S20, a determination is made as to whether the address of the memory cell is a final address (a step S28). If the address is not the final address, then the address is incremented (a step S30), and the processing returns to the step S14. That is, erase verifying is made in accordance with the incremented address. If the data of the memory cell in the final address is verified in the step S28, then a read instruction is written into the status register 235 and the instruction register 237 in order to reset the registers 235 and 237 (a step S32), and the erase cycle is ended.
As described above, in the erase cycle, if the memory cell data is unerased, then the erase pulse width TEW is incremented and an erasing sequence is repeated. A verification sequence is started from a final unerased memory cell.
FIG. 15 is a flow chart showing an operation during programming. A description will now be made on a programming operation of the nonvolatile semiconductor memory device with reference to FIGS. 12, 13 and 15.
A programming cycle is started by external application of a high voltage Vpp of 12 V (a step S52) and initialization of the pulse counter.
Then, a program setup instruction is written into the instruction register 237 and the status register 235 (a step S54), and external address bits A0-Am and data are subsequently latched (a step S56). After the data and address are latched, data writing into an addressed memory cell is carried out under control by the instruction port controller 2. When a predetermined time period T1 has passed (a step S58), a program verify instruction is written into the instruction register 237 and the status register 235 (a step S60). A program verify voltage is generated from the erase/program verification generator 9 in accordance with the program verify instruction and then applied via the X decoder 12 onto a word line connecting the addressed memory cell. After a predetermined time period (T2) has passed (a step S62), data is read from the addressed memory cell in order to verify the programmed data (a step S64).
The data reading is realized by falling of the output enable signal /OE to a low level. A determination is made as to whether the read data is equal to the program data (a step S66). If they are not equal to each other, the pulse count PLSCNT is incremented to extend a program time, and a determination is made as to whether this pulse number PLSCNT is a predetermined value (23). If the pulse number is lower than the predetermined value, the processing returns to the step S54, and the program sequence is again executed (a step S68).
If the pulse number PLSCNT does not reach the predetermined value (23) in the step S68, it is determined that the memory cell is unprogrammable, and a program error is stored (a step S70). That is, repetitive applying of pulses of a predetermined width up to the times of a maximum count value of 25 causes extension of the programming time. When this programming time reaches a predetermined value, a program error of the nonvolatile semiconductor memory device is detected.
If the read data and the program data match each other in the step S66, it is determined whether to program another byte data (a step S72). If it is determined that data should be written into another byte in the step S72, the next address is latched, and a program sequence from the step S52 is repeated (a step S74). If a final address of the memory cell to be programmed is reached in the step S72, then a read instruction is written into the status register 235 and the instruction register 237 to bring both registers 235 and 237 in a reset state.
The programming sequence shown in FIG. 15 is utilized also as an operation sequence (for the step S4) in which data "00H" is written into all the memory cells in the erase sequence shown in FIG. 14, so as to bring all the memory cells in a programmed state and adjust their threshold voltages.
In the nonvolatile semiconductor memory device as described above, erasing of memory cell data is made by electrically drawing electrons from the floating gate by a tunneling current. In this case, as shown in FIG. 16, electrons are excessively drawn out from the floating gate 106, so that such a state appears that the floating gate 106 is charged positively. This state is called an over-erase state. In the over-erase state, the positive charges stored in the floating gate 106 cause electrons to be attracted to the surface of the channel region 112. Even if the control gate 108 is held at a ground potential, this channel region 112 appears and the memory cells are always in an ON state (depletion state) as shown by broken lines in FIG. 11.
Usually, in order to prevent such an over-erase state, the data "00H" is written into all the memory cells at the initial stage of the erase cycle and their threshold voltages are equally set to a sufficiently large value. The erasing operation is thereafter carried out. When unerased memory cells are detected in the erase cycle, however, erase pulses are applied to all the memory cells and the erase sequence is repeated. Thus, since an erase voltage is also applied to erased memory cells, the over-erase state inevitably occurs. Problems of such over-erased memory cells will now be described with reference to FIG. 17.
In FIG. 17, memory cells MC1, MC2 and MC3 provided at intersections of three word lines WL1, WL2 and WL3 and a single bit line BL are shown only for the purpose of illustration. Assume that the memory cell MC1 stores data "1" in the erase state, the memory cell MC2 is in the over-erase state, and the memory cell MC3 stores data "0" in the program state. A case is now considered where storage data "1" of the memory cell MC1 is read. In this case, a potential of the word line WL1 rises to a logic high level, and the word lines WL2 and WL3 are at a ground potential. In this case, since the memory cell MC1 stores data "1" therein and a current flows through the bit line BL, the data "1" is read. No problems occur in this state.
When the data of the memory cell MC3 is read, the potential of the word line WL3 is set at a logic high level, and the word lines WL1 and WL2 are held at the ground potential. In this case, the memory cell MC3 stores data "0" therein and is in an OFF state. Since the memory cell MC2 is in the over-erase state, however, a current flows from the bit line BL through this memory cell MC2 to a source S even if the potential of the word line WL2 is the ground potential. It is this determined that the memory cell MC3 is storing the data "1", and erroneous data reading is carried out. Accordingly, when there is any memory cell in the over-erase state, a problem occurs that data reading is not ensured.
Such a memory cell in the over-erase state is produced due to influences exerted by local effects in the memory array (i.e., the degree of a film thickness of a gate insulating film or the degree of capacitance coupling between the control gate 108 and the floating gate 106) even if the erase pulse application number is smaller. When there is such a memory cell in the over-erase state, since an accurate data programming and reading cannot be carried out even if other memory cells are in a normal state, the semiconductor memory device is disposed as a defective product, resulting in a decrease in the production yield of the semiconductor memory device.